AK8854VQ Datasheet, PDF (70/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
Output Control Register (R/W) [Sub Address 0x07], for output pin output status setting
Sub Address 0x07
bit 7
bit 6
bit 5
bit 4
CLKINV
DVALID_FSEL VD_FSEL
HL
Default Value
0
0
0
0
Default Value: 0x00
bit 3
bit 2
bit 1
bit 0
NL
DVALID_FL VD_FL
DL
0
0
0
0
Output Control Register Definition
Bit Register Name
bit 0 DL
D Output Low bit
bit 1 VD_FL
VD/FIELD Low bit
bit 2 DVALID_FL
DVALID/FIELD Low bit
bit 3 NL
NSIG Low bit
bit 4 HL
HD Low bit
bit 5 VD_FSEL
VD/FIELD Select bit
bit 6 DVALID_FSEL DVALID/FIELD Select bit
bit 7 CLKINV
CLK Invert Set bit
R/W Definition
R/W
[0]: Normal output
[1]: [D7: D0] pin output fixed at Low
R/W
[0]: Normal output
[1]: VD_F pin output fixed at Low
R/W
[0]: Normal output
[1]: DVALID_F pin output fixed at Low
R/W
[0]: Normal output
[1]: NSIG pin output fixed at Low
R/W
[0]: Normal output
[1]: HD pin output fixed at Low
VD_F pin output signal selection
R/W _{[0]: VD signal output}
[1]: FIELD signal output
DVALID_F pin output signal selection
R/W _{[0]: DVALID signal output}
[1]: FIELD signal output
DTCLK signal output polarity selection
[0]: Normal output
R/W
(write in data at rising edge)
[1]: Data and clock reversed
(write in data at falling edge)
Note: Output control via pins OE, PDN, and RSTN takes priority, regardless of the above settings.
MS0973-E-01
70
2008/07