AK8854VQ Datasheet, PDF (73/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
bit 5
~
CSDLY[2:0] CSYNC Dealy
bit 7
Setting for timing between external sync signal and
RGB signal.
[CSDLY2: CSDLY0]
[000]: No delay and No advance between external
sync signal and RGB signal
[001]: External sync signal has 1 pixel delay from
RGB signal.
[010]: External sync signal has 2 pixel delay from
RGB signal.
R/W [011]: External sync signal has 3 pixel delay from
RGB signal.
[100]: External sync signal has 4 pixel delay from
RGB signal.
[101]: External sync signal has 3 pixels advance from
RGB signal.
[110]: External sync signal has 2 pixels advance from
RGB signal.
[111]: External sync signal has 1 pixels advance from
RGB signal.
*It is prohibited that vertical sync interval of external sync signal is 1 line or 2 lines.
MS0973-E-01
73
2008/07