AK8854VQ Datasheet, PDF (50/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
7.17.1.2 Fixed-clock mode
In fixed-clock mode, operation is at an internally generated 27 MHz clock, from a 24.576 MHz input clock.
The output signal is therefore not synchronized with the input signal, and thus not ITU- BT.656 compliant.
Data is output in SAV format. As shown in the following figure, EAV is guaranteed for 720 pixels from
SAV, but the sample number from EAV to SAV is not.
SAV
EAV
720 pixels
858 / 864 ( NTSC / PAL ) pixels ± α
7.17.2 DVALID and timing signal interface
For connection with devices having no ITU-R.BT.656 interface, the AK8854 DVALID signal output
identifies the active video interval by remaining low throughout that period, as shown in the following
figure.
In fixed-clock mode, the internal clock is not synchronized with the output signal, but a space of 122/132
(NTSC/PAL) pixels is guaranteed between the horizontal sync signal and the start of the active video
interval.
122/132 Pixels
Video Signal
HSYNC
DVALID
CLK27MOUT
D[7:0]
‘’’’ ^{Cb0 Y0 Cr0 Y1 Cb1 Y2 Cr1 Y3}
Y718 Cr359 Y719
Active Video Start Position
ʢ௨ৗ
఺͔Β
MS0973-E-01
50
2008/07