AK8854VQ Datasheet, PDF (66/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
Component Setting Control Register (R/W) [Sub Address 0x03], for YPbPr and RGB
Sub Address 0x03
bit 7
bit 6
Reserved CSY1
Default Value
0
0
bit 5
CSY0
0
bit 4
RGBSS1
0
bit 3
bit 2
RGBSS0 CSCL
0
0
Default Value: 0x00
bit 1
bit 0
CSSL
ALLSYNC
0
0
Component Setting Control Register Definition
Bit
Register
Name
R/W
bit 0 ALLSYNC
ALL Sync Select R / W
bit 1 CSSL
bit 2 CSCL
bit 3 RGBSS0
~
~
bit 4 RGBSS1
Component Signal
Sync Level
R/W
Component Signal
Chroma Level
R/W
RGB Sync Select R / W
bit 5 CSY0
~
~
bit 6 CSY1
bit 7 Reserved
CSYNC SELECT R / W
Reserved
R/W
Definition
Setting for sync signal of RGB input.
[External sync is Sync On Green]
[0]: R and B signals don’t contain sync signal.
[1]: All RGB signals don’t contain sync signal.
[External sync is CSYNC orH/VSYNC]
[0]: R and G signals also contain sync signal.
[1]: All RGB signals contain sync signal.
Setting for sync level of YPbPr or RGB
[0]: 300mV
[1]: 286mV
Setting for clolr change level
[0]: 700mV support
[1]: 714mV support
Setting for sync signal of RGB input.
[ RGBSS1: RGBSS0 ]
[00]: Sync On Green
[01]: CSYNC
[10]: H/VSYNC
[00]: Reserved
Setting for external sync signal.
[ CSY1: CSY0 ]
[00]:CSYNC1 ~ 4
[01]:CSYNC5H/VSYNC
[10]:CSYNC6
[11]: Reserved
Reserved
MS0973-E-01
66
2008/07