AK8854VQ Datasheet, PDF (21/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
6. Functional overview
The following key functions are characteristic of the AK8854 and its operational performance.
(1) It accepts composite video signal (CVBS), S-video, component YPbPr and RGB input with 10 input
pins available for this purpose. The decode signal is selected via the register.
(2) It contains an internal analog band limiting filter (anti-aliasing) in front of the AD converter input.
(3) Its analog circuit clamps the input signal to the sync tip (analog sync tip clamp). Its digital circuit
clamps the digitized input data to the pedestal level (digital pedestal clamp).
(4) It decodes NTSC-M,ç J; NTSC-4.43; PAL-B, D, G, H, I, N; PAL-Nc, PAL-M, PAL-60; and SECAM
video signals, as selected by register setting for input signal category.
In auto detection mode, it automatically recognizes the input signal category.
(5) Its VBI data slicing function enables output of the slicing results as ITU-R BT.601 format digital
data.
(6) Its adaptive AGC function enables measurement of the input signal size and determination of the
input signal level.
(7) Its ACC function enables measurement of the input signal color burst size and determination of the
appropriate color burst level.
(8) It performs adaptive two-dimensional Y/C separation, in which its phase detector selects the best
correlation from among vertical, horizontal, and diagonal samples and the optimum Y/C separation
mode.
(9) Its digital pixel spacing adjustor can align vertical positions by vertical pixel positioning.
(10) It operates in line-locked, frame-locked, or fixed clock mode, with automatic transition and optimum
mode selection by automatic scanning.
(11) In PAL-B, D, G, H, I, and N decoding, it can perform phase-difference correction for each line.
(12) Its decoded data is ITU-R BT.656 compliant, except in certain cases of fixed-clock operation or
poor-quality input signal.
(13) For connection of devices having no ITU-R BT.656 interface, it shows the active video region by
DVALID signal output.
(14) Its input-stage embedded PGA can be adjusted in the range -6~+6dB by register setting, in gain
steps of approximately 0.1 dB/step.
(15) It detects and separates the sync signal from the digitized input signal. The detected sync signal
provides the base timing for decode processing, and the separated sync signal as the basis for
calculation of phase error signal and for sampling clock control.
(16) It judges the chroma signal quality from the color burst of the input signal, and can apply color kill if
the signal quality is judged insufficient.
It can also apply color kill if the color decode PLL lock is lost.
(17) Its image quality adjustment function includes contrast, brightness, hue, color saturation, and
sharpness adjustment.
(18) Its luminance band limiting filter is adjustable via register setting.
(19) It can provide sepia output of decoded results.
(20) It can decode conflated closed caption data, closed caption extended data, VBID(CGMS), and
WSS signals, and write them separately to the storage register.
(21) Its monitoring register enables monitoring of a number of internal functions.
(22) It enables Macrovision signal type notification, in cases where the Macrovision signal is included in
the decoded data.
(23) It enables U/V signal band adjustment, by switching the low pass filter after C signal demodulating.
(24) It enables C filter band switching via the register, for Y/C separation.
MS0973-E-01
21
2008/07