AK8854VQ Datasheet, PDF (39/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
VLSTR[1:0]-bit: Setting for start position at vertical sync interval of external sync signal.
It is effective only CSY=[01] or [10].
VLSTR-bit
Start line
525 line (Odd/ Even)
625 line (Odd/ Even)
Notes
[00]
Line 4 / Line 266.5
Line 1/ Line 313.5
[01]
Line 3 / Line 265.5
Line 625/ Line 312.5
Refer to fig.1 ~ 4 for line
[10]
Line 2 / Line 264.5
Line 624/ Line 311.5
number
[11]
Line 1 / Line 263.5
Line 623/ Line 310.5
VLSTP[2:0]-bit: Setting for end position at vertical sync interval of external sync signal.
It is effective only CSY=[01] or [10].
VLSTP-bit
End line
525 line (Odd/ Even)
625 line (Odd/ Even)
Notes
[000]
Line 4 / Line 266.5
Line 1/ Line 313.5
[001]
Line 5 / Line 267.5
Line 2/ Line 314.5
[010]
[011]
[100]
Line 6 / Line 268.5
Line 7 / Line 269.5
Line 8 / Line 270.5
Line 3/ Line 315.5
Line 4/ Line 316.5
Line 5/ Line 317.5
Refer to fig.1 ~ 4 for line
number
[101]
Line 9 / Line 271.5
Line 6/ Line 318.5
[110]
Line 10 / Line 272.5
Line 7/ Line 319.5
For example, the settings for wave forms ofCSYNC5,CSYNC6 in Fig.1 ~ 4 are VLSTR=[11] and
VLSTP=[110]. The settings for wave forms ofH/VSYNC in Fig.1 ~ 4 are VLSTR=[00] and VLSTP=[010].
*It is prohibited that vertical sync interval of external sync signal is 1 line or 2 lines.
CSDLY[2:0]-bit: Setting for timing between external sync signal and RGB signal.
CSYDLY-bit Timing
[000]
[001]
[010]
[011]
[100]
[101]
[110]
[111]
No delay and No advance between external sync signal and RGB signal
External sync signal has 1 pixel delay from RGB signal.
External sync signal has 2 pixels delay from RGB signal.
External sync signal has 3 pixels delay from RGB signal.
External sync signal has 4 pixels delay from RGB signal.
External sync signal has 3 pixels advance from RGB signal.
External sync signal has 2 pixels advance from RGB signal.
External sync signal has 1 pixel advance from RGB signal.
Notes
MS0973-E-01
39
2008/07