AK8854VQ Datasheet, PDF (74/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
AGC & ACC Control Register (R/W) [Sub Address 0x0A], for AGC and ACC setting
Sub Address 0x0A
bit 7
bit 6
ACCFRZ ACC1
Default Value
0
0
bit 5
ACC0
0
bit 4
bit 3
AGCFRZ AGCC1
0
0
bit 2
AGCC0
0
Default Value: 0x00
bit 1
bit 0
AGCT1
AGCT0
0
0
AGC & ACC Control Register Definition
Bit
Register
Name
bit 0 AGCT0
~
~
bit 1 AGCT1
AGC Time Constant
bit 2 AGCC0
~
~
bit 3 AGCC1
AGC Coring Control
bit 4 AGCFRZ
AGC Freeze
bit 5 ACC0
~
~
bit 6 ACC1
ACC Time Constant
bit 7 ACCFRZ
ACC Freeze
R/W Definition
AGC time constant (T) setting*
(if disabled, PGA can be set manually)
[AGCT1: AGCT0]
R/W _{[00]: Disable}
[01]: Fast [T = 1 field]
[10]: Middle [T = 7 fields]
[11]: Slow [T = 29 fields ]
AGC non-sensing bandwidth (LSB) setting
[AGCC1: AGCC0]
R/W
[00]: ±2 LSB
[01]: ±3 LSB
[10]: ±4 LSB
[11]: No non-sensing band
AGC freeze function (ON/OFF) setting
R/W
(AGC set values are saved during freeze)
[0]: Non-frozen
[1]: Frozen
ACC time constant (T) setting
[ACCT1: ACCT0]
R/W
[00]: Disable
[01]: Fast [T = 2Fields]
[10]: Middle [T =8Fields]
[11]: Slow [T = 30Fields]
ACC freeze function (ON/OFF) setting
R/W
(ACC set values are saved during freeze)
[0] : Non-frozen
[1] : Frozen
AGCT must be set “disable” when sync signal is H/VSYNC or CSYNC at RGB input.
MS0973-E-01
74
2008/07