AK8854VQ Datasheet, PDF (75/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
Control 0 Register (R/W) [Sub Address 0x0B], for the following function setting
Sub Address 0x0B
bit 7
bit 6
DVALID_FP VD_FP
Default Value
0
0
bit 5
HDP
0
bit 4
C443FIL0
bit 3
C443FIL0
bit 2
C358FIL1
Default Value: 0x00
bit 1
bit 0
C358FIL0 AGCTL
0
0
0
0
0
Control 0 Register Definition
Bit
Register
Name
R/W Definition
Transition speed setting, between peak AGC
bit 0 AGCTL
AGC Transition Level
R/W
and sync AGC
[0]: Quick
[1]: Slow
C-filter bandwidth setting, for 3.58 MHz
subcarrier system signal
bit 1 C358FIL0
[C358FIL1: C358FIL0]
~
~
C Filter_358 Select bit
R/W [00]: 3.58 Narrow
bit 2 C358FIL1
[01]: 3.58 Medium
[10]: 3.58 Wide
[11]: Reserved
C-filter bandwidth setting, for 4.43 MHz
subcarrier system signal
bit 3 C443FIL0
[C443FIL1: C443FIL0]
~
~
C Filter_443 Select bit
R/W [00]: 4.43 Narrow
bit 4 C443FIL1
[01]: 4.43 Medium
[10]: 4.43 Wide
[11]: Reserved
HD signal polarity setting
bit 5 HDP
HD Pin Polarity Set bit
R/W [0]: Active Low
[1]: Active High
VD_F pin output polarity setting
If in VD signal output mode
[0]: Active Low
bit 6 VD_FP
VD_F Pin Polarity Set bit
R/W
[1]: Active High
If in field signal output mode
[0]: Odd-Field Low, Even-Field High
[1]: Even-Field Low, Odd-Field High
DVALID_F pin output signal polarity setting
If in DVALID signal output mode
[0]: Active Low
bit 7 DVALID_FP DVALID_F Pin Polarity Set bit R/W
[1]: Active High
If in field signal output mode
[0]: Odd-field Low, Even-field High
[1]: Even-field Low, Odd-field High
MS0973-E-01
75
2008/07