AK8854VQ Datasheet, PDF (71/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
Start and Delay Control Register (R/W) [Sub Address 0x08], for data output setting
Sub Address 0x08
bit 7
bit 6
Reserved ACTSTA2
Default Value
0
0
bit 5
ACTSTA1
0
bit 4
bit 3
bit 2
ACTSTA0 Reserved Reserved
0
0
0
Default Value: 0x00
bit 1
bit 0
Reserved Reserved
0
0
Start and Delay Control Register Definition
Bit
Register
Name
R/W
bit 0 YCDELAY0
~
~
Y/C Delay Control
R/W
bit 2 YCDELAY2
bit 3 Reserved Reserved
R/W
bit 4 ACTSTA0
~
~
Active Video Start Control bit R/W
bit 6 ACTSTA2
bit 7 Reserved Reserved
R/W
Definition
Adjustment of Y and C timing.
[ YCDELAY2 : YCDELAY0 ]
[001] : Y advance 1sample toward C.
[010] : Y advance 2sample toward C.
[011] : Y advance 3sample toward C.
[000] : No Delay and advance.
[101] : Y delay 3 sample toward C.
[110] : Y delay 2 sample toward C.
[111] : Y delay 1 sample toward C.
[100] : Reserved
Reserved
Fine-tuning video data decode start position
by delay or advance in 1-sample units 1
sample clock (13.5 MHz; approx. 74 ns)
[ACTSTA2: ACTSTA0]
[001]: 1-sample delay
[010]: 2-sample delay
[011]: 3-sample delay
[000]: Normal start position
[101]: 3-sample advance
[110]: 2-sample advance
[111]: 1-sample advance
[100]: Reserved
Reserved
MS0973-E-01
71
2008/07