AK8854VQ Datasheet, PDF (72/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
CSYNC Delay Control Register (R/W) [Sub Address 0x09] for external signal setting
Sub Address 0x09
bit 7
bit 6
CSDLY2 CSDLY1
Default Value
0
0
bit 5
CSDLY0
0
bit 4
VLSTP2
0
bit 3
VLSTP1
1
bit 2
VLSTP0
0
Default Value : 0x08
bit 1
bit 0
VLSTR1 VLSTR0
0
0
CSYNC Delay Control Register Definition
Bit
Register
Name
bit 0
~
VLSTR[1:0] Vsync Line Start
bit 1
bit 2
~ VLSTP[2:0] Vsync Line Stop
bit 4
R/W Definition
Setting for start position at vertical sync
interval of external sync signal. It is effective
only CSY=[01] or [10].
[VLSTR1: VLSTR0]
525 Line case (ODD/EVEN)
[00] : Line 4/ Line 266.5
R/W
[01] : Line 3/ Line 265.5
[10] : Line 2/ Line 264.5
[11] : Line 1/ Line 263.5
625Line case (ODD/EVEN)
[00] : Line 1/ Line 313.5
[01] : Line 625/ Line 312.5
[10] : Line 624/ Line 311.5
[11] : Line 623/ Line 310.5
Setting for end position at vertical sync
interval of external sync signal. It is effective
only CSY=[01] or [10].
[VLSTP2: VLSTP0]
525 Line case (ODD/EVEN)
[000]: Line 4/ Line 266.5
[001]: Line 5/ Line 267.5
[010]: Line 6/ Line 268.5
[011]: Line 7/ Line 269.5
R/W
[100]: Line 8/ Line 270.5
[101]: Line 9/ Line 271.5
[110]: Line 10/ Line 272.5
625 Line case (ODD/EVEN)
[000]: Line 1/ Line 313.5
[001]: Line 2/ Line 314.5
[010]: Line 3/ Line 315.5
[011]: Line 4/ Line 316.5
[100]: Line 5/ Line 317.5
[101]: Line 6/ Line 318.5
[110]: Line 7/ Line 319.5
MS0973-E-01
72
2008/07