AK8854VQ Datasheet, PDF (64/95 Pages) Asahi Kasei Microsystems – Multi-Format Digital Video Decoder

[AK8854VQ]
AFE Control Register 1 (R/W) [Sub Address 0x01], for analog front end
Sub Address 0x01
bit 7
bit 6
CLPWIDTH1 CLPWIDTH0
Default Value
0
0
bit 5
bit 4
CLPSTAT1 CLPSTAT0
0
0
bit 3
Reserved
Default Value : 0x00
bit 2
bit 1
bit 0
BCLPSTAT2 BCLPSTAT1 BCLPSTAT0
0
0
0
0
AFE Control Register 1 Definition
Bit Register Name
bit 0 BCLPSTAT0
~
~
bit 2 BCLPSTAT2
Back Porch Clamp Start
bit 3 Reserved
Reserved
bit 4 CLPSTAT0
~
~
bit 5 CLPSTAT1
Clamp Start
bit 6 CLPWIDTH0
~
~
bit 7 CLPWIDTH1
Clamp Pulse Width
R/W
R/W
R
R/W
R/W
Definition
Set the position of analog backporch clamp pulse.
[ BCLPSTAT2 : BCLPSTAT0 ]
[000]: Same position with “CLPSTAT” setting
[001]: (1/128)H delay from “CLPSTAT” setting
[010]: (2/128)H delay from “CLPSTAT” setting
[011]: (3/128)H delay from “CLPSTAT” setting
[100]: (4/128)H advance from “CLPSTAT” setting
[101]: (3/128)H advance from “CLPSTAT” setting
[110]: (2/128)H advance from “CLPSTAT” setting
[111]: (1/128)H advance from “CLPSTAT” setting
Reserved
Set the position of clamp pulse
[ CLPSTAT1 : CLPSTAT0 ]
[00] : Sync tip/ middle/ bottom clamp:
Centor of horizontal sync
Back porch clamp:
Centor of backporch interval
[01] : (1/128) H delay
[10] : (2/128) H advance
[11] : (1/128) H advance
Set the width of clamp pulse.
[ CLPWIDTH1 : CLPWIDTH0 ]
[00] : 275nsec
[01] : 555nsec
[10] : 1.1usec
[11] : 2.2usec
MS0973-E-01
64
2008/07