AK4537 Datasheet, PDF (74/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
Date (YY/MM/DD) Revision Reason
03/05/23
02
Explanation
addition:
Page Contents
27
Manual Mode
“When writing to the IPGAL6-0 and
IPGAR6-0 bits continually, the control
register should be written by an interval more
than zero crossing timeout (the write
operation interval between IPGAL6-0 and
IPGAR6-0 bits also should be more than zero
crossing timeout). When IPGAC bit is “0”, the
write operation interval from IPGAL6-0 bits
to IPGAR6-0 bits is no care. Therefore, the
auto increment function of I²C bus is available
at IPGAC = “0”.” is added.
28
Example of ALC1 Operation
“IPGA gain at ALC1 operation start can be
changed from the default value of IPGAL6-0
bits while PMMICL, PMMICR, PMIPGL or
PMIPGR bit is “1” and ALC1 bit is “0”. When
ALC1 bit is changed from “1” to “0”, IPGA
holds the last gain value set by ALC1
operation.” is added.
43
Register Definitions (PMBPM bit)
“Even if PMBPM= “0”, the path is still
connected between BEEPM and HP-Amp.
BPMHP bit should be set to “0” to disconnect
this path.”
→ “Even if PMBPM= “0”, the path is still
connected between BEEPM and HP/SPK-Amp.
BPMHP and BPMSP bits should be set to “0” to
disconnect these paths, respectively.”
43
Register Definitions (PMBPS bit)
“Even if PMBPS= “0”, the path is still
connected between BEEPL/R and HP-Amp.
BPSHP bit should be set to “0” to disconnect
this path.”
→ “Even if PMBPS= “0”, the path is still
connected between BEEPL/R and
HP/SPK-Amp. BPSHP and BPSSP bits should
be set to “0” to disconnect these paths,
respectively.”
44
Register Definitions (Addr=00H)
“IPGA gain is reset when
PMMICL=PMMICR=PMIPGL=PMIPGR=
“0”.” is added.
“The paths from BEEP to HP-Amp and
SPK-Amp can operate without these clocks.” is
added.
MS0202-E-04
- 74 -
2005/04