AK4537 Datasheet, PDF (45/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
PMVCM: VCOM Block Power Control
0: Power down (Default)
1: Power up
Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are
powered down.
When all bits except MCKPD bit are “0” in the 00H, 01H and 10H addresses, all blocks are powered down. The
register values remain unchanged. IPGA gain is reset when PMMICL=PMMICR=PMIPGL=PMIPGR= “0” (refer
to the IPGAL6-0 and IPGAR6-0 bits description).
When any of the blocks are powered up, the PMVCM bit must be set to “1”.
MCLK, BICK and LRCK must always be present unless PMMICL=PMMICR=PMIPGL=PMIPGR=PMADCL
=PMADR=PMDAC=PMSPK= “0” or PDN pin = “L”. The paths from BEEP to HP-Amp and SPK-Amp can
operate without these clocks.
Addr
01H
Register Name
Power Management 2
R/W
Default
D7
MCKPD
R/W
1
D6
PMXTL
R/W
0
D5
PMPLL
R/W
0
D4
SPKG
R/W
0
PMDAC: DAC Block Power Control
0: Power down (Default)
1: Power up
PMHPR: Rch of Headphone-Amp Common Voltage Power Control
0: Power down (Default)
1: Power up
PMHPL: Lch of Headphone-Amp Common Voltage Power Control
0: Power down (Default)
1: Power up
PMSPK: Speaker Block Power Control
0: Power down (Default)
1: Power up
SPKG: Select Speaker-Amp Output Power (8Ω load)
0: 150mW (Default)
1: 300mW(ALC2 = “0”) or 250mW(ALC2 = “1”)
PMPLL: PLL Block Power Control Select
0: EXT Mode and Power down (Default)
1: PLL Mode and Power up
PMXTL: X’tal Oscillation Block Power Control
0: Power down (Default)
1: Power up
MCKPD: XTI pin pull down control
0: Master Clock input enable
1: Pull down by 25kΩ (Default)
D3
PMSPK
R/W
0
D2
PMHPL
R/W
0
D1
PMHPR
R/W
0
D0
PMDAC
R/W
0
MS0202-E-04
- 45 -
2005/04