AK4537 Datasheet, PDF (12/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
DC CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V)
Parameter
Symbol
min
typ
Max
Units
High-Level Input Voltage
VIH 70%DVDD
-
-
V
Low-Level Input Voltage
VIL
-
-
30%DVDD V
Input Voltage at AC Coupling
(Note 25)
VAC 50%DVDD
-
-
V
High-Level Output Voltage
(Iout=−200µA) VOH DVDD−0.2
-
-
V
Low-Level Output Voltage
(Except SDA pin: Iout=200µA) VOL
-
-
0.2
V
(SDA pin: Iout=3mA) VOL
-
-
0.4
V
Input Leakage Current
Iin
-
-
±10
µA
Note 25. When AC coupled capacitor is connected to MCKI pin.
SWITCHING CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; C_L=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Crystal Resonator Frequency
11.2896
-
12.288
MHz
External Clock Frequency
fCLK
2.048
-
12.288
MHz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
ns
Pulse Width High
tCLKH 0.4/fCLK
-
-
ns
AC Pulse Width (Note 26) tACW 0.4/fCLK
-
-
ns
MCKO Output
Frequency
fMCK
0.256
-
12.288
MHz
Duty Cycle: except fs=32kHz
dMCK
40
fs=32kHz at 256fs (Note 27)
dMCK
-
50
60
%
33
-
%
LRCK Timing
Frequency
fs
8
-
48
kHz
Duty Cycle
Slave mode
Duty
45
-
55
%
Master mode
Duty
-
50
-
%
Audio Interface Timing
Slave mode
BICK Period
tBCK
312.5
-
BICK Pulse Width Low
tBCKL
130
-
Pulse Width High
tBCKH
130
-
LRCK Edge to BICK “↑”
(Note 28)
tLRB
50
-
BICK “↑” to LRCK Edge
(Note 28)
tBLR
50
-
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
-
-
BICK “↓” to SDTO
tBSD
-
-
SDTI Hold Time
tSDH
50
-
SDTI Setup Time
tSDS
50
-
-
ns
-
ns
-
ns
-
ns
-
ns
80
ns
80
ns
-
ns
-
ns
Master mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
(BF bit = “0”) fBCK
-
64fs
-
Hz
(BF bit = “1”) fBCK
-
32fs
-
Hz
dBCK
-
50
-
%
tMBLR
−80
-
80
ns
tBSD
−80
-
80
ns
tSDH
50
-
-
ns
tSDS
50
-
-
ns
Note 26. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to
ground (Refer to Figure 4).
Note 27. PMPLL bit = “1”.
Note 28. BICK rising edge must not occur at the same time as LRCK edge.
MS0202-E-04
- 12 -
2005/04