AK4537 Datasheet, PDF (13/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
Parameter
Symbol
min
Control Interface Timing (4-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
CDTO Delay
CSN “↑” to CDTO Hi-Z
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
tDCD
-
tCCZ
-
fSCL
-
Bus Free Time Between Transmissions
tBUF
4.7
Start Condition Hold Time (prior to first clock pulse) tHD:STA
4.0
Clock Low Time
tLOW
4.7
Clock High Time
tHIGH
4.0
Setup Time for Repeated Start Condition
tSU:STA
4.7
SDA Hold Time from SCL Falling
(Note 29) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.25
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
4.0
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Reset Timing
PDN Pulse Width
(Note 30)
tPD
150
PMADL or PMADR “↑” to SDTO valid (Note 31)
tPDV
-
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2081
Note 29. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 30. The AK4537 can be reset by the PDN pin = “L”.
Note 31. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
max
Units
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
50
ns
70
ns
100
kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
1.0
µs
0.3
µs
-
µs
50
ns
-
ns
-
1/fs
MS0202-E-04
- 13 -
2005/04