AK4537 Datasheet, PDF (69/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
„ Stop of Clock
MCLK can be stopped when PMMIC=PMADC=PMDAC=PMSPK= “0”.
1. When X’tal is used in PLL mode
MCKO bit
(Addr:03H, D4)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKPD bit
(Addr:01H, D7)
(1)
(2)
E xam ple :
A udio I/F Form at : I²S
BIC K frequency at M aster M ode : 64fs
Input M aster C lock S elect at P LL M ode : 11.2896M H z
O utput M aster C lock Frequency : 64fs
(1) Addr:04H , D ata:62H
(2) Addr:01H , D ata:80H
Figure 57. Stop of Clock Sequence(1)
<Example>
(1) Disable MCKO output : MCKO bit = “1” → “0”
(2) Power down X’tal and PLL, Pull down the XTI pin :
PMXTL bit = PMPLL bit = “1” → “0”, MCKPD = “0” → “1”
2. When an external clock is used in PLL mode
MCKO bit
(Addr:03H, D4)
PMPLL bit
(Addr:01H, D5)
MCKPD bit
(Addr:01H, D7)
External MCLK
(1)
(2)
(3)
Input
E xam ple :
A udio I/F : I²S
BICK frequency at M aster M ode : 64fs
Input M aster C lock S elect at P LL M ode : 11.2896M H z
O utput M aster C lock F requency : 64fs
(1) Addr:04H , D ata:62H
(2) Addr:01H , D ata:80H
(3) Stop external clock
Figure 58. Stop of Clock Sequence(2)
<Example>
(1) Stop MCKO output : MCKO bit = “1” → “0”
(2) Power down PLL, Pull down the XTI pin : PMPLL bit = “1” → “0”, MCKPD = “0” → “1”
When the external MCLK becomes Hi-Z or the external MCLK is input by AC couple, MCKI pin should be
pulled down.
(3) Stop an external MCLK
MS0202-E-04
- 69 -
2005/04