AK4537 Datasheet, PDF (36/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
„ Stereo Line Output (LOUT/ROUT pins)
MIC In
0dB/+20dB
ATT
IPGA Lch
“DAHS”
ATT+DAC
[AK4537]
“MICL”
LOUT pin
ROUT pin
Figure 31. Stereo Line Output
When DAHS bit is “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins which is single-ended. When
MICL bit is “1”, Lch signal of IPGA is output from LOUT/ROU pins. The load impedance is 10kΩ (min.). When the
PMLO bit is “0”, the stereo line output enters power-down-mode and the output is placed in a Hi-Z state. When the PSLO
bit is “0” at PMLO bit is “1”, stereo line output becomes power-save-mode and the LOUT/ROUT pins are forced to 0.45
x AVDD voltage. When PSLO bit is “1” at PMLO bit is “1”, stereo line output is normal operation.
ATTL7-0 and ATTR7-0 bits set the volume control of DAC output. ATTS3-0 bits set the volume control of IPGA Lch
output.
„ Mono Output (MOUT+/MOUT- pins)
MIC In
0dB/+20dB
ATT
IPGA Lch
ATT+DAC
“DAMO”
1/2
1/2
“MICM”
“MOGN”
-17dB/+6dB
Figure 32. Mono Line Output
MOUT+
MOUT-
When DAMO bit is “1”, mono mixer mixes Lch and Rch signal from DAC. This mixed signal is output to mono line
output that is differential output. When MICM bit is “1”, Lch signal from IPGA is output to mono line output. Either
MOUT+ or MOUT- pin can be used as single-ended output pin. The load impedance is 20kΩ (min.). When the PMMO bit
is “0”, the mono line output enters power-down-mode and the output is placed in a Hi-Z state.
ATTL7-0 and ATTR7-0 bits set the volume control of DAC output. ATTM bit sets the volume control of IPGA Lch
output. Amp for mono line output has 6dB gain and -17dB gain that are set by the MOGN bit.
MS0202-E-04
- 36 -
2005/04