AK4537 Datasheet, PDF (24/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
„ System Reset
Upon power-up, reset the AK4537 by bringing the PDN pin = “L”. This ensures that all internal registers reset to their
initial values.
The ADC enters an initialization cycle that starts when the PMADL or PMADR bit is changed from “0” to “1”. The
initialization cycle time is 2081/fs, or 47.2ms@fs=44.1kHz. During the initialization cycle, the ADC digital data outputs
of both channels are forced to a 2's compliment, “0”. The ADC output reflects the analog input signal after the
initialization cycle is complete. The DAC does not require an initialization cycle.
„ Audio Interface Format
Three types of data formats are available and are selected by setting the DIF1-0 bits (Table 13). In all modes, the serial
data is MSB first, 2’s complement format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched
on the rising edge. All data formats can be used in both master and slave modes. LRCK and BICK are output from
AK4537 in master mode, but must be input to AK4537 in slave mode. If 16-bit data that ADC outputs is converted to 8-bit
data by removing LSB 8-bit, −1 at 16bit data is converted to −1 at 8-bit data. And when the DAC playbacks this 8-bit data,
−1 at 8-bit data will be converted to −256 at 16-bit data and this is a large offset. This offset can be removed by adding the
offset of 128 to 16-bit data before converting to 8-bit data. When ADC is used as monaural, the output data of
powered-down channel is “0”.
When LOOP bit = “1”, audio interface format of SDTO is fixed to I²S regardless of DIF1-0 bits setting.
Mode
0
1
2
3
DIF1
0
0
1
1
DIF0
0
1
0
1
SDTO (ADC) SDTI (DAC)
MSB justified LSB justified
MSB justified
I²S
MSB justified
I²S
N/A
N/A
Table 13. Audio Interface Format
BICK
≥ 32fs
≥ 32fs
≥ 32fs
N/A
Figure
Figure 16
Figure 17
Figure 18
-
Default
LRCK
0123
BICK(32fs)
SDTO(o)
15 14 13
9 10 11 12 13 14 15 0 1 2 3
7 6 5 4 3 2 1 0 15 14 13
9 10 11 12 13 14 15 0 1
7 6 5 4 3 2 1 0 15
SDTI(i)
15 14 13
0123
BICK(64fs)
SDTO(o)
15 14 13
7 6 5 4 3 2 1 0 15 14 13
15 16 17 18
31 0 1 2 3
10
15 14 13
7 6 5 4 3 2 1 0 15
15 16 17 18
31 0 1
10
15
SDTI(i)
Don't Care
15:MSB, 0:LSB
15 14
Lch Data
10
Don't Care
15 14 2 1 0
Rch Data
Figure 16. Mode 0 Timing
MS0202-E-04
- 24 -
2005/04