AK4537 Datasheet, PDF (22/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
MCKI pin
MCKO pin
BICK pin
LRCK pin
Master Mode (M/S pin = “H”)
Power up
Power down PLL Unlock
Frequency set by PLL1-0
bits (Refer to Table 2)
Refer to Table 1
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
“L”
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
BF bit = “0” : 64fs Output
BF bit = “1” : 32fs Output
“L”
“L”
Output
“L”
“L”
Table 5. Clock Operation at Master Mode (PLL Mode)
MCKI pin
MCKO pin
BICK pin
LRCK pin
Slave Mode (M/S pin = “L”)
Power up
Power down
PLL Unlock
Frequency set by PLL1-0
bits (Refer to Table 2)
Refer to Table 1
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
“L”
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
Input
Fixed to “L” or “H” externally
Input
Input
Fixed to “L” or “H” externally
Input
Table 6. Clock Operation at Slave Mode (PLL Mode)
(2) External mode (PMPLL bit = “0”)
When the PMPLL bit = “0”, the AK4537 works in external clock mode. The MCKO pin outputs a buffered clock of
MCKI input.
For example, when MCKI = 256fs, the sampling frequency is changeable from 8kHz to 48kHz (Table 7). The MCKO bit
controls MCKO output enable. The frequency of MCKO is selectable via register the PS1-0 bits as defined in Table 8. If
PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input in slave mode. The master clock frequency should be changed only when the PMADL, PMADR and
PMDAC bits = “0”.
LRCK and BICK are output from the AK4537 in master mode. The clock to the MCKI pin must not stop during normal
operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If this clock is not provided, the AK4537 may
draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the
AK4537 in power-down mode (PMADL bit = PMADR bit = PMDAC bit = “0”).
MCKI, BICK and LRCK clocks are required in slave mode. The master clock (MCKI) should be synchronized with
sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK should always be present
whenever the AK4537 is in normal operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks
are not provided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic. If the
external clocks are not present, place the AK4537 in power-down mode (PMADL bit = PMADR bit = PMDAC bit = “0”).
Mode
0
1
2
3
FS1
FS0
Sampling Frequency (fs)
0
0
8kHz ∼ 48kHz
0
1
8kHz ∼ 24kHz
1
0
8kHz ∼ 12kHz
1
1
N/A
Table 7. Sampling Frequency Select (EXT Mode)
MCKI
256fs
512fs
1024fs
N/A
Default
MS0202-E-04
- 22 -
2005/04