AK4537 Datasheet, PDF (62/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
„ Clock Set up
When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCLK, BICK and LRCK) must be supplied.
1. When X'tal is used in PLL mode. (Slave mode)
MCKPD bit
(Addr:01H, D7)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
MCKO pin
BICK, LRCK
(Slave Mode)
PS1-0 bits
(Addr:04H, D5-4)
(1)
20ms(typ) ⁽²⁾
40ms(max)
(3)
00
E xam p le :
A udio I/F Fo rm at : I²S
B IC K freq ue ncy at M a ste r M o de : 64fs
I np u t M a s t e r C lo c k S e le c t a t P L L M o d e : 1 1 .2 8 9 6 M H z
O utp u t M a s te r C lo c k F re q ue n c y : 6 4 f s
(1 ) A d d r:0 1 H , D ata:4 0 H
(2 ) A d d r:0 1 H , D ata:6 0 H
(4)
Output
(5)
Input
(6)
XX
(3 ) A d d r:0 4 H , D ata 4 A H
(4 ) M C K O ou tpu t starts
(5 ) B IC K and L R C K inp u t start
(6 ) A d d r:0 4 H , D ata 6 A H
Figure 49. Clock Set Up Sequence(1)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1” → “0” and power-up the X’tal oscillator: PMXTL bit
= “0” → “1”
(2) Power-up the PLL : PMPLL bit = “0” → “1”
The PLL should be powered-up after the X’tal oscillator becomes stable. It takes X’tal oscillator 20ms(typ) to
be stable after PMXTL bit=“1”. This time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0”
→ “1”.
(3) Enable MCKO output : MCKO bit = “0” → “1”
(4) MCKO is output after PLL becomes stable.
(5) Input BICK and LRCK synchronized with the MCKO output.
(6) Set the MCKO output frequency (PS1-0 bits)
If PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input.
MS0202-E-04
- 62 -
2005/04