AK4537 Datasheet, PDF (44/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
„ Register Definitions
Addr
00H
Register Name
Power Management 1
R/W
Default
D7
PMVCM
R/W
0
D6
PMBPS
R/W
0
D5
PMBPM
R/W
0
D4
PMLO
R/W
0
D3
PMMO
R/W
0
D2
PMIPGL
R/W
0
D1
PMMICL
R/W
0
D0
PMADL
R/W
0
PMADL: ADC Lch Block Power Control
0: Power down (Default)
1: Power up
When the PMADL or PMADR bit changes from “0” to “1”, the initialization cycle (2081/fs=47.2ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMADL
0
0
1
1
PMADR
Analog
Lch
Rch
0
Power down Power down
1
Power down Power up
0
Power up Power down
1
Power up
Power up
Table 22. ADC Block Power Control
Digital
L/R
Power down
Power up
Power up
Power up
PMMICL: MIC Power and IPGA Lch Block Power Control
0: Power down (Default)
1: Power up
PMIPGL: IPGA Lch Block Power Control
0: Power down (Default)
1: Power up
IPGA Lch Block is powered up if PMMICL or PMIPGL bit is “1” (see Table 23).
PMMICL PMIPGL MIC-Amp
IPGA
0
0
Power down Power down
0
1
Power down
Power up
1
0
Power up
Power up
1
1
Power up
Power up
Table 23. MIC-Amp and IPGA Lch Block Power Control
PMMO: Mono Line Out Power Control
0: Power down (Default)
1: Power up
PMLO: Stereo Line Out Power Control
0: Power down (Default)
1: Power up
PMBPM: Mono BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPM= “0”, the path is still connected between BEEPM and HP/SPK-Amp. BPMHP and BPMSP
bits should be set to “0” to disconnect these paths, respectively.
PMBPS: Stereo BEEP In Power Control
0: Power down (Default)
1: Power up
Even if PMBPS= “0”, the path is still connected between BEEPL/R and HP/SPK-Amp. BPSHP and BPSSP
bits should be set to “0” to disconnect these paths, respectively.
MS0202-E-04
- 44 -
2005/04