AK4537 Datasheet, PDF (27/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
„ Manual Mode
The AK4537 becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below.
1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc)
2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed.
For example; When the change of the sampling frequency.
3. When IPGA is used as a manual volume.
When writing to the IPGAL6-0 and IPGAR6-0 bits continually, the control register should be written by an interval more
than zero crossing timeout (the write operation interval between IPGAL6-0 and IPGAR6-0 bits also should be more than
zero crossing timeout). When IPGAC bit is “0”, the write operation interval from IPGAL6-0 bits to IPGAR6-0 bits is no
care. Therefore, the auto increment function of I²C bus is available at IPGAC = “0”.
„ MIC-ALC Operation
The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is “1”. When PMMICL bit =
“1” and PMMIR bit = “1”, the IPGA is set to the same value for both channels.
[1] ALC1 Limiter Operation
When the ALC1 limiter is enabled, and IPGA Lch or Rch output exceeds the ALC1 limiter detection level (LMTH), the
IPGA value is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically.
When the ZELM bit = “1”, the timeout period is set by the LTM1-0 bits. The operation for attenuation is done
continuously until both Lch and Rch input signal levels become LMTH or less. If the ALC1 bit does not change into “0”
after completing the attenuation, the attenuation operation repeats while Lch or Rch input signal level equals or exceeds
LMTH.
When the ZELM bit = “0”, the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation
function so that the IPGA value is attenuated at the zero-detect points of the waveform.
[2] ALC1 Recovery Operation
The ALC1 recovery refers to the amount of time that the AK4537 will allow both Lch and Rch signal to exceed a
predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits
to define the wait period used after completing an ALC1 limiter operation. If Lch or Rch input signals are lower than the
“ALC1 Recovery Waiting Counter Reset Level”, the ALC1 recovery operation starts. The IPGA value increases
automatically during this operation up to the reference level (REF6-0 bits). The ALC1 recovery operation is done at a
period set by the WTM1-0 bits. Zero crossing is detected during WTM1-0 period, the ALC1 recovery operation waits
WTM1-0 period and the next recovery operation starts.
During the ALC1 recovery operation, when Lch or Rch input signal level exceeds the ALC1 limiter detection level
(LMTH), the ALC1 recovery operation changes immediately into an ALC1 limiter operation.
In the case of
(IPGA Lch and Rch Output Level) < (Limiter detection level)
and
(IPGA Lch and Rch Output Level) ≥ (Recovery waiting counter reset level)
during the ALC1 recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of
(IPGA Lch or Rch Output Level) < (Recovery waiting counter reset level),
the wait timer for the ALC1 recovery operation starts.
The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation
becomes faster than a normal recovery operation.
MS0202-E-04
- 27 -
2005/04