AK4537 Datasheet, PDF (58/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
10H Power Management 3
0
0
0
INR
INL PMIPGR PMMICR PMADR
R/W
RD
RD
RD
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
PMADR: ADC Rch Block Power Control
0: Power down (Default)
1: Power up
When the PMADL or PMADR bit changes from “0” to “1”, the initialization cycle (2081/fs = 47.2ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
PMADL
0
0
1
1
PMADR
Analog
Lch
Rch
0
Power down Power down
1
Power down Power up
0
Power up Power down
1
Power up
Power up
Table 34. ADC Block Power Control
Digital
L/R
Power down
Power up
Power up
Power up
PMMICR: MIC Power and IPGA Rch Block Power Control
0: Power down (Default)
1: Power up
PMIPGR: IPGA Rch Block Power Control
0: Power down (Default)
1: Power up
IPGA Rch Block is powered up if PMMICR or PMIPGR bit is “1” (see Table 35).
PMMICR PMIPGR MIC-Amp
IPGA
0
0
Power down Power down
0
1
Power down
Power up
1
0
Power up
Power up
1
1
Power up
Power up
Table 35. MIC-Amp and IPGA Rch Block Power Control
INL: IPGA Lch Input Select
0: MIC input (LIN1: Default)
1: LINE input (LIN2)
INR: IPGA Rch Input Select
0: MIC input (RIN1: Default)
1: LINE input (RIN2)
MS0202-E-04
- 58 -
2005/04