AK4537 Datasheet, PDF (56/76 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Stereo CODEC with MIC/HP/SPK-AMP

ASAHI KASEI
[AK4537]
Addr
0BH
0FH
Register Name
Lch Input PGA Control
Rch Input PGA Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
IPGAL6 IPGAL5 IPGAL4 IPGAL3 IPGAL2 IPGAL1 IPGAL0
0
IPGAR6 IPGAR5 IPGAR4 IPGAR3 IPGAR2 IPGAR1 IPGAR0
RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
0
0
0
IPGAL6-0: Lch Input Analog PGA (see Table 32)
IPGAR6-0: Rch Input Analog PGA (see Table 32)
Default: “10H” (0dB)
When IPGA gain is changed, IPGAL6-0 and IPGAR6-0 bits should be written while PMMICL, PMMICR,
PMIPGL or PMIPGR bit is “1” and ALC1 bit is “0”. IPGA gain is reset when PMMICL=PMMICR=PMIPGL
=PMIPGR= “0”, and then IPGA operation starts from the default value when PMMICL, PMMICR, PMIPGL
or PMIPGR bit is changed to “1”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value
set by ALC1 operation. When IPGAL6-0 and IPGAR6-0 bits are read, the register values written by the last
write operation are read out regardless the actual gain.
DATA (HEX)
47
46
45
:
36
:
2F
:
10
:
06
05
04
03
02
01
00
GAIN (dB)
MIC Input
LINE Input
+27.5
+12.0
+27.0
+11.5
+26.5
+11.0
:
:
+19.0
+3.5
:
:
+15.5
+0.0
:
:
+0.0
-15.5
:
:
−5.0
−20.5
−5.5
−21.0
−6.0
−21.5
−6.5
−22.0
−7.0
−22.5
−7.5
−23.0
−8.0
−23.5
Table 32. Input Gain Setting
STEP
0.5dB
Default
Addr
0CH
0DH
Register Name
Lch Digital ATT Control
Rch Digital ATT Control
R/W
Default
D7
ATTL7
ATTR7
R/W
0
D6
ATTL6
ATTR6
R/W
0
D5
ATTL5
ATTR5
R/W
0
D4
ATTL4
ATTR4
R/W
0
D3
ATTL3
ATTR3
R/W
0
D2
ATTL2
ATTR2
R/W
0
D1
ATTL1
ATTR1
R/W
0
D0
ATTL0
ATTR0
R/W
0
ATTL/R7-0: Digital ATT Output Control (see Table 18)
Default: “00H” (0dB)
MS0202-E-04
- 56 -
2005/04