Z8018008VSG Datasheet, PDF (78/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
72
MMU Common/Bank Area Register (CBAR)
Mnemonic CBAR
Address 3A
CBAR specifies boundaries within the Z80180 64-KB logical address space for up to three
areas: Common Area, Bank Area and Common
Area 1.
MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
7
6
5
4
Bit
CA3
CA2 CA1
CA0
R/W
R/W
R/W
R/W
3
BA3
R/W
2
BA2
R/W
1
BA1
R/W
0
BA0
R/W
Figure 75. MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH
CA3–CA0:CA (bits 7-4)—CA specifies the start (Low) address
(on 4 KB boundaries) for the Common Area 1, and also determines the most recent address
of the Bank Area. All bits of CA are set to 1 during RESET.
BA–BA0 (bits 3-0)—BA specifies the start (Low) address (on 4-KB boundaries) for the
Bank Area, and also determines the most recent address of the Common Area 0. All bits of
BA are set to 1 during RESET.
Operation Mode Control Register
Mnemonic OMCR
Address 3E
The Z80180 is descended from two different ancestor processors, ZiLOG's original Z80 and
the Hitachi 64180. The Operating Mode
PS014004-1106
Architecture