Z8018008VSG Datasheet, PDF (66/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
60
DMA Memory Address Register, Channel 1H
Mnemonic MAR1H: Address 29h
DMA Memory Address Register, Channel 1H
76 54 32 1 0
—— —— — — — —
DMA Memory Address
Figure 59. DMA Memory Address Register, Channel 1H
DMA Memory Address Register, Channel 1B
Mnemonic MAR1B (Address 2A)
DMA
32 1 0
——— —
DMA Memory Channel B Address
Figure 60. DMA Memory Address Register, Channel 1B
DMA I/O Address Register Channel 1
(IAR1: I/O ADDRESS = 2Bh to 2Dh) specifies the I/O address for channel 1 transfers, which
may also be a destination or source I/O address. The
register contains 16 bits of I/O address; its most significant byte identifies the REQUEST
HANDSHAKE signal and controls the Alternating Channel feature.
All bits in IAR1B reset to 0.
PS014004-1106
Architecture