Z8018008VSG Datasheet, PDF (14/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
8
Table 2. Pin Status During RESET BUSACK and SLEEP(continued) (continued)
Pin Number and
Package Type
QFP PLCC DIP
61 60
56
62
63
64 61
57
65 62
58
66 63
59
67 64
60
68 65
61
69 66
62
70 67
63
71 68
64
72 1
1
73 2
74 3
2
75
76 4
3
77 5
4
78 6
5
79 7
6
80 8
7
Default
Function
HALT
NC
NC
RFSH
IORQ
MREQ
E
M1
WR
RD
PHI
V_SS
V_SS
XTAL
NC
EXTAL
WAIT
BUSACK
BUSREQ
RESET
Pin Status
Secondary
Function RESET BUSACK
1
1
1
1
1
0
1
1
1
OUT
GND
GND
OUT
OUT
3T
3T
OUT
1
3T
3T
OUT
GND
GND
OUT
IN
IN
IN
IN
1
OUT
IN
IN
IN
IN
SLEEP
0
OUT
1
1
OUT
1
1
1
OUT
GND
GND
OUT
IN
IN
OUT
IN
IN
Pin Descriptions
A0–A19. Address Bus (output, active High, 3-state)—A₀–A₁₉ form a 20-bit address bus.
The address bus provides the address for memory data bus exchanges, up to 1 MB, and I/O
data bus exchanges, up to 64 KB. The address bus enters a high-impedance state during reset
and external bus acknowledge cycles. Address line A18 is multiplexed with the output of
programmable reload timer (PRT) channel 1 (T_OUT, selected as address output on reset) and
address line A19 is not available in DIP versions of the Z80180.
PS014004-1106
Overview