Z8018008VSG Datasheet, PDF (55/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
49
Timer Reload Register 0L
RLDR0L: 0EH
Timer Reload Register Low
0Eh
76 54 32 1
—— —— — — —
Timer Reload Data
Figure 39. Timer Reload Register Low
Timer Reload Register 0H
RLDR0H
Timer Reload Register
0Fh
76 54 32 1
—— —— — — —
Timer Reload Data
Figure 40. Timer Reload Register
Timer Control Register (TCR)
TCR monitors both channels (PRT0, PRT1) TMDR status. It also controls enabling and
disabling of down counting and interrupts along with controlling output pin A18/T_OUT for
PRT1.
Timer Control Register (TCR: I/O Address = 10h)
Bit
7
6
5
4
3
2
1
0
TIF1
R
TIF0
R
TIE1
R/W
TIE0
R/W
TOC1
R/W
TOC0
R/W
TDE1
R/W
TDE0
R/W
Figure 41. Timer Control Register (TCR: I/O Address = 10h)
PS014004-1106
Architecture