Z8018008VSG Datasheet, PDF (58/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
52
Break Detect (bit 1)—The receiver sets this READ-ONLY bit to 1 when an all-zero
character with a Framing Error becomes the oldest character in the RxFIFO. The bit is
cleared when software writes a 0 to the EFR bit in CNTLA register, also by RESET, by
IOSTOP mode, and for ASCIO if the DCD0 pin is auto-enabled and is negated (High).
Send Break (bit 0)—If this bit and bit 2 are both 1, the transmitter holds the TXA pin Low
to send a break condition. The duration of the break is under software control (one of the
PRTs or CTCs can be used to time it). This bit resets to 0, in which state TXA carries the
serial output of the transmitter.
Timer Data Register Channel 1L
Mnemonic TMDR1L:14H
Timer Data Register
76 54 32 1 0
Timer Data
Figure 43. Timer Data Register Channel 1L
Timer Data Register Channel 1H
Mnemonic TMDR1H: 15H
Timer Data Register
76 54 32 1 0
Timer Data
Figure 44. Timer Data Register Channel 1H
PS014004-1106
Architecture