Z8018008VSG Datasheet, PDF (75/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
69
TRAP Timing—3^rd Op Code Undefined
φ
A₀–A₁₈ (A₁₉)
D₀–D₇
M1
MREQ
RD
WR
3nd Opcode Memory
Fetch Cycle READ Cycle
PC Stacking
Restart
from 0000h
Opcode
Fetch Cycle
T₁ T₂ T₃ T₁ T₂ T_TP T₃ T_i T_i T_i T_i T₁ T₂ T₃ T₁ T₂ T₃ T₁ T₂ T₃
PC
IX + d, IY + d
Undefined
Opcode
SP-1
PC-1_H
SP-2
PC-1_L
0000h
Figure 71. TRAP Timing—3^rd Opcode Undefined
Refresh Control Register
Mnemonic RCR (Address 36)
Refresh Control Register (RCA: I/O Address = 36h)
7- 6
——
54
——
32
——
10
——
REFE
REFW
Reserved
Cyc0
Cyc1
Figure 72. Refresh Control Register (RCA: I/O Address = 36h)
The RCR specifies the interval and length of refresh cycles, while enabling or disabling the
refresh function.
REFE: Refresh Enable (bit 7)— REFE = 0 disables the refresh controller, while
REFE = 1 enables refresh cycle insertion. REFE is set to 1 during RESET.
REFW: Refresh Wait (bit 6)—REFW = 0 causes the refresh cycle to be two clocks in
duration. REFW = 1 causes the refresh cycle to be three clocks in duration by adding a
refresh wait cycle (TRW). REFW is set to 1 during RESET.
PS014004-1106
Architecture