Z8018008VSG Datasheet, PDF (16/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
10
interrupt before operation resumes. It is also used with the M1 and ST signals to decode
status of the CPU machine cycle.
INT0—Maskable Interrupt Request 0 (input, active Low). This signal is generated by exter-
nal I/O devices. The CPU honors these requests at the end of the current instruction cycle as
long as the NMI and BUSREQ
signals are inactive. The CPU acknowledges this interrupt request with an interrupt
acknowledge cycle. During this cycle, both the M1 and IORQ signals become active.
INT1, INT2—Maskable Interrupt Request 1 and 2 (inputs, active Low). This signal is gener-
ated by external I/O devices. The CPU honors these requests at the end of the current
instruction cycle as long as the NMI, BUSREQ, and INT0 signals are inactive. The CPU
acknowledges these requests with an interrupt acknowledge cycle. Unlike the acknowledg-
ment for INT0, during this cycle neither the M1 or IORQ signals become active.
IORQ—I/O Request (output, active Low, 3-state). IORQ indicates that the address bus con-
tains a valid I/O address for an I/O READ or I/O WRITE operation. IORQ is also generated,
along with M1, during the acknowledgment of the INT0 input signal to indicate that an inter-
rupt response vector can be placed onto the data bus. This signal is analogous to the IOE sig-
nal of the Z64180.
M1—Machine Cycle 1 (output, active Low). Together with MREQ, M1 indicates that the cur-
rent cycle is the opcode fetch cycle of and instruction execution. Together with IORQ, M1
indicates that the current cycle is for an interrupt acknowledge. It is also used with the HALT
and ST signal to decode status of the CPU machine cycle. This signal is analogous to the LIR
signal of the Z64180.
MREQ—Memory Request (output, active Low, 3-state). MREQ indicates that the address
bus holds a valid address for a memory READ or memory WRITE operation. This signal is
analogous to the ME signal of Z64180.
NMI—Nonmaskable Interrupt (input, negative edge triggered). NMI demands a higher prior-
ity than INT and is always recognized at the end of an instruction, regardless of the state of
the interrupt enable flip-flops. This signal forces CPU execution to continue at location
0066h.
RD—Opcode Reinitialized (output, active Low, 3-state). RD indicated that the CPU wants to
read data from memory or an I/O device. The addressed I/O or memory device must use this
signal to gate data onto the CPU data bus.
RFSH—Refresh (output, active Low). Together with MREQ, RFSH indicates that the current
CPU machine cycle and the contents of the address bus must be used for refresh of dynamic
memories. The low order 8 bits of the address bus (A7–A10) contain the refresh address.
This signal is analogous to the REF signal of the Z64180.
RTS0—Request to Send 0 (output, active Low). A programmable modem control signal for
ASCI channel 0.
RXA0, RXA1—Receive Data 0 and 1 (input, active High). These signals are the receive data
to the ASCI channels.
PS014004-1106
Overview