Z8018008VSG Datasheet, PDF (44/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
38
ASCI Block Diagram
TXA₀
RXA₀
RTS₀
CTS₀
DCD₀
ASCI Transmit Data Register
Ch 0: TDR0
ASCI Transmit Shift Register*
Ch 0: TSR0
ASCI Receive Data FIFO
Ch 0: RDR0
ASCI Receive Shift Register*
Ch 0: RSR0 (8)
ASCI Control Register A
Ch 0: CNTLA0 (8)
ASCI Control Register B
Ch 0: CNTB0 (8)
ASCI Status FIFO
Ch 0
ASCI Status Register
Ch 0: STAT0 (8)
Internal Address/Data Bus
Interrupt Request
ASCI
Control
ASCI Transmit Data Register
Ch 1: TDR1
ASCI Transmit Shift Register*
Ch 1: TSR1
ASCI Receive Data FIFO
Ch 1: RDR1
ASCI Receive Shift Register*
Ch 1: RSR1 (8)
ASCI Control Register A
Ch 1: CNTLA1 (8)
ASCI Control Register B
Ch 1: CNTB1 (8)
ASCI Status FIFO
Ch 1
ASCI Status Register
Ch 1: STAT1 (8)
TXA₁
RXA₁
CTS₁
CKA₀
CKA₁
Baud Rate
Generator 0
φ
Baud Rate
Generator 1
Note: *Not Program
Accessible.
Figure 27. ASCI Block Diagram
ASCI Registers
ASCI Transmit Shift Register 0 (TSR0, TSR1)—When the ASCI Transmit Shift
Register (TSR) receives data from the ASCI Transmit Data Register (TDR), the data is
shifted out to the TxA pin. When transmission is completed, the next byte (if available) is
automatically loaded from TDR into TSR and the next transmission starts. If no data is
available for transmission, TSR IDLEs by outputting a continuous High level. This
register is not program accessible.
ASCI Transmit Data Register 0,1 (TDR0, TDR1)— I/O
address = 06h, 07h. Data written to the ASCI Transmit Data Register is
transferred to the TSR as soon as TSR is empty. Data can be written while TSR is shifting out
the previous byte of data. The ASCI transmitter is double buffered.
PS014004-1106
Architecture