Z8018008VSG Datasheet, PDF (51/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
45
ASCI Status Register 0, 1 (STAT0, 1)
Each channel status register allows interrogation of ASCI communication, error and modem
control signal status, and enabling or disabling of ASCI interrupts.
ASCI Status Registers
ASCI Status Register 0 (STAT0: I/O Address = 04h)
Bit 7
6
5
4
3
2
1
0
RDRF OVRN PE
R
R
R
FE
RE DCD₀ TDRE TIE
R R/W
R
R
R/W
ASCI Status Register 1 (STAT1: I/O Address = 05h)
Bit 7
6
5
4
3
2
1
0
RDRF OVRN PE
R
R
R
FE
RE
__ _TDRE TIE
R
R/W
R
R/W
Figure 34. ASCI Status Registers
RDRF: Receive Data Register Full (bit 7)—RDRF is set to 1 when an incoming data
byte is loaded into an empty RxFIFO.
Note: ^{If a framing or parity error occurs, RDRF is still set and the receive data (which}
generated the error) is still loaded into the FIFO.
RDRF is cleared to 0 by reading RDR and most recent character in the FIFO from IOSTOP
mode, during RESET and for ASCI0 if the DCD0 input is auto-enabled and is negated (High).
OVRN: Overrun Error (bit 6)—An overrun condition occurs when the receiver finishes
assembling a character, but the RxFIFO is full so that there is no room for the character.
However, this status bit is not set until the most recent character received before the overrun
becomes the oldest byte in the FIFO. This bit is cleared when software writes a 1 to the EFR
bit in the CNTLA register, and also by RESET, in IOSTOP mode, and for ASCI0 if the DCD0
pin is auto enabled and is negated (High).
When an overrun occurs, the receiver does not place the character in the shift register into
the FIFO, nor any subsequent characters, until the last good character comes to the top of the
FIFO so that OVRN is set, and software then writes a 1 to EFR to clear it.
PE: Parity Error (bit 5)—A parity error is detected when parity checking is enabled by
the MOD1 bit in the CNT1LA register being 1, and a character is assembled in which the
parity does not match the PEO bit in the CNTLB register. However, this status bit is not set
until or unless the error character becomes the oldest one in the RxFIFO. PE is cleared when
software writes a 1 to the EFR bit in the CNTRLA register, and also by RESET, in IOSTOP
mode, and for ASCI0 if the DCD0 pin is auto-enabled and is negated (High).
PS014004-1106
Architecture