Z8018008VSG Datasheet, PDF (73/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
67
Int/TRAP Control Register
Mnemonics ITC
Address 34
INT/TRAP Control Register (ITC, I/O Address 34h)
This register is used in handling TRAP interrupts and to enable or disable Maskable Interrupt
Level 0 and the INT1 and INT2 pins.
Bit ⁷
6
5
4
3
2
1
0
TRAP UFO –– –– –– ITE2 ITE1 ITE0
R/W R
R/W R/W R/W
Figure 69. Int/TRAP Control Register
TRAP (bit 7)—This bit is set to 1 when an undefined opcode is fetched. TRAP can be reset
under program control by writing it with a 0, however, it cannot be written with 1 under pro-
gram control. TRAP is reset to 0 during RESET.
UFO: Undefined Fetch Object (bit 6)—When a TRAP interrupt occurs, the contents of
a UFO allow the starting address of the undefined instruction to be determined. However, the
TRAP may occur on either the second or third byte of the opcode. A UFO allows the stacked
Program Counter (PC) value to be correctly adjusted. If UFO = 0, the first opcode must be
interpreted as the stacked PC-1. If UFO = 1, the first opcode address is stacked PC-2. UFO is
READ-ONLY.
ITE2, 1, 0: Interrupt Enable 2, 1, 0 (bits 2-0)—ITE2 and ITE1 enable and disable the
external interrupt inputs INT2 and INT1, respectively. ITE0 enables and disables interrupts
from the on-chip ESCC, CTCs and bidirectional Centronics controller as well as the external
interrupt input INT0. A 1 in a bit enables the corresponding interrupt level while a 0 disables
it. A RESET clears ITE0 to 1 and clears ITE1 and ITE2 to 0.
TRAP Interrupt
The Z80180 generates a nonmaskable (not affected by the state of IEF1) TRAP interrupt
when an undefined opcode fetch occurs. This feature can be used to increase software reli-
ability, implement an extended instruction set, or both. TRAP may occur during opcode fetch
cycles and also if an undefined opcode is fetched during the interrupt acknowledge cycle for
INT0 when Mode 0 is used.
PS014004-1106
Architecture