Z8018008VSG Datasheet, PDF (23/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
17
T₁
T₂
T₃
T₁
T₂
T₃
f
WR
M1
WRITE into OMCR
Opcode Fetch
Figure 10. M1 Temporary Enable Timing
IOC—This bit controls the timing of the IORQ and RD signals. It is set to 1 by RESET. When
IOC = 1, the IORQ and RD signals function the same as the Z64180 (Figure 11).
T₁
φ
T₂
T_W
T₃
IORQ
RD
WR
Figure 11. I/O READ and WRITE Cycles with IOC = 1
When IOC = 0, the timing of the IORQ and RD signals match the timing of the Z80. The
IORQ and RD signals go active as a result of the rising edge of T2 (see Figure 12).
T₁
φ
IORQ
T₂
T_W
T₃
RD
WR
Figure 12. I/O READ and WRITE Cycles with IOC = 0
PS014004-1106
Architecture