Z8018008VSG Datasheet, PDF (29/85 Pages) Zilog, Inc. – Microprocessor Unit

Table 7. Z80180-6 AC Characteristics (continued)
No Symbol Item
20 t_WH
21 t_WDZ
22 t_WRD1
23 t_WDD
24 t_WDS
25 t_WRD2
26 t_WRP
26a
WAIT Hold Time from Ø Fall
Ø Rise to Data Float Delay
Ø Rise to WR Fall Delay
Ø Fall to WRITE Data Delay Time
WRITE Data Set-up Time to WR Fall
Ø Fall to WR Rise Delay
WR Pulse Width
WR Pulse Width (I/O WRITE Cycle)
27 t_WDH
28 t_IOD1
WRITE Data Hold Time from (WR Rise)
Ø Fall to IORQ Fall Delay IOC = 1
Ø Rise to IORQ Fall Delay IOC = 1
29 t_IOD2 Ø Fall to IORQ Rise Delay
30 t_IOD3 M1 Fall to IORQ Fall Delay
31 t_INTS INT Set-up Time to Ø Fall
32 t_INTS INT Hold Time from Ø Fall
33 t_NMIW NMI Pulse Width
34 t_BRS BUSREQ Set-up Time to Ø Fall
35 t_BRH BUSREQ Hold Time from Ø Fall
36 t_BAD1 Ø Rise to BUSACK Fall Delay
37 t_BAD2 Ø Fall to BUSACK Rise Delay
38 t_BZD Ø Rise to Bus Floating Delay Time
39 t_MEWH MREQ Pulse Width (High)
40 t_MEWL MREQ Pulse Width (Low)
41 t_RFD1 Ø Rise to RFSH Fall Delay
42 t_RFD2 Ø Rise to RFSH Rise Delay
43 t_HAD1 Ø Rise to HALT Fall Delay
44 t_HAD2 Ø Rise to HALT Rise Delay
45 t_DRQS /DREQi Set-up Time to Ø Rise
46 t_DRQH /DREQi Hold Time from Ø Rise
47 t_TED1 Ø Fall to TENDi Fall Delay
48 t_TED2 Ø Fall to TENDi Rise Delay
49 t_ED1 Ø Rise to E Rise Delay
50 t_ED2 Ø Fall or Rise to E Fall Delay
51 P_WEH E Pulse Width (High)
52 P_WEL E Pulse Width (Low)
53 t_Er
Enable Rise Time
54 t_Ef
Enable Fall Time
PS014004-1106
Z80180
Microprocessor Unit
23
Z80180-6
Min Max Unit
40 –
ns
– 95 ns
– 65 ns
– 90 ns
40 –
ns
– 80 ns
170 –
ns
332 –
ns
40 –
– 60 ns
– 65
– 60 ns
340 –
ns
40 –
ns
40 –
ns
120 –
ns
40 –
ns
40 –
ns
– 95 ns
– 90 ns
– 125 ns
110 –
ns
125 –
ns
– 90 ns
– 90 ns
– 90 ns
– 90 ns
40 –
ns
40 –
ns
– 70 ns
– 70 ns
– 95 ns
– 95 ns
75 –
ns
180 –
ns
– 20 ns
– 20 ns
Architecture