Z8018008VSG Datasheet, PDF (56/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
50
TIF1: Timer Interrupt Flag 1 (bit 7)—When TMDR1 decrements to 0, TIF1 is set to 1,
and, when enabled by TIE1 = 1, an interrupt request is generated. TIF1 is reset to 0 when TCR
is read and the higher or lower byte of TMDR1 is read. During RESET, TIF1 is cleared to 0.
TIF0: Timer Interrupt Flag 0 (bit 6)—When TMDR0 decrements to 0, TIF0 is set to 1,
and, when enabled by TIE0 = 1, an interrupt request is generated TIF0 is reset to 0 when TCR
is read and the higher or lower byte of TMDR0 is read. During RESET, TIF0 is cleared to 0.
TIE1: Timer Interrupt Enable 1 (bit 5)—When TIE0 is set to 1, TIF1 = 1 generates a
CPU interrupt request. When TIE0 is reset to 0, the interrupt request is inhibited. During
RESET, TIE0 is cleared to 0.
TOC1, 0: Timer Output Control (bits 3, 2)—TOC1 and TOC0
control the output of PRT1 using the multiplexed T_OUT/DREQ pin as
indicated in Table 14. During RESET, TOC1 and TOC0 are cleared to 0. If bit 3 of the IAR1B
register is 1, the T_OUT function is selected. By
programming TOC1 and TOC0, the T_OUT/DREQ pin can be forced High, Low, or toggled
when TMDR1 decrements to 0.
Table 14. Timer Output Control
TOC1
0
0
1
1
TOC0
0
1
0
1
Output
Inhibited
Toggled
0
1
The T_OUT/DREQ pin is not affected by the
PRT.
If bit 3 of IAR1B is 1, the T_OUT/DREQ pin
toggles or is set Low or High as indicated.
TDE1, 0: Timer Down Count Enable (bits 1, 0)—TDE1 and TDE0 enable and disable
down counting for TMDR1 and TMDR0, respectively. When TDEn (N = 0,1) is set to 1, down
counting is stopped and TMDRn is freely read or written. TDE1 and TDE0 are cleared to 0
during RESET and TMDRn do not decrement until TDEn is set to 1.
ASCI Extension Control Register Channels 0 and 1
ASEXT0 and ASEXT1
The ASCI Extension Control Register controls functions newly added to the ASCIs in the
Z80180 family.
Note: All bits in this register reset to 0.
PS014004-1106
Architecture