Z8018008VSG Datasheet, PDF (46/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
40
Channel 1
Mnemonics TDR1 (Address (07h)
76 54 32 1
—- — —- — — — —
ASCI Transmit Channel 1
Figure 29. ASCI Register Channel 1
ASCI Receive Registers
Register addresses 08h and 09h hold the ASCI receive data for channel 0 and channel 1,
respectively.
Channel 0
Mnemonics TSR0 (Address (08h)
ASCI Receive Register Channel 0
76 54 32 1
—— —— — — —
ASCI Receive Data
Figure 30. ASCI Receive Register Channel 0
PS014004-1106
Architecture