Z8018008VSG Datasheet, PDF (37/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
31
PHI
ADDRESS
WAIT
MREQ
IORQ
RD
WR
M1
Opcode Fetch Cycle
T₁
T₂
23
T_W
T₃
4
5
1
6
I/O Write Cycle*
I/O Read Cycle*
T₁
T₂
T_W
T₃
T₁
19 ²⁰ 19 ²⁰
7
12 11
8
7
29 11
11
13
28
13
9
9
11
22
25
26
14
10
ST
17
Data IN
Data OUT
62
RESET
63
18
15
16
23
24
15
21
16
27
62
63
68
67
67
68
Figure 16. CPU Timing (Opcode Fetch, I/O WRITE, and I/O READ Cycles)
PS014004-1106
Architecture