Z8018008VSG Datasheet, PDF (53/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
47
clears EF to 0 when TRDR is read or written. EF is cleared to 0 during RESET and IOSTOP
mode.
EIE: End Interrupt Enable (bit 6)—EIE is set to 1 to generate a CPU interrupt request.
The interrupt request is inhibited if EIE is reset to 0. EIE is cleared to 0 during RESET.
RE: Receive Enable (bit 5)—A CSIO receive operation is started by setting RE to 1.
When RE is set to 1, the data clock is enabled. In internal clock mode, the data clock is out-
put from the CKS pin. In external clock mode, the clock is input on the CKS pin. In either
case, data is shifted in on the RXS pin in synchronization with the (internal or external) data
clock. After receiving 8 bits of data, the CSIO automatically clears RE to 0, EF is set to 1, and
an interrupt (if enabled by EIE = 1) is generated. RE and TE are never both set to 1 at the
same time. RE is cleared to 0 during RESET and ISTOP mode.
Transmit Enable (bit 4)—A CSIO transmit operation is started by setting TE to 1. When
TE is set to 1, the data clock is enabled. When in internal clock mode, the data clock is out-
put from the CKS pin. In external clock mode, the clock is input on the CKS pin. In either
case, data is shifted out on the TXS pin synchronous with the (internal or external) data
clock. After transmitting 8 bits of data, the CSIO automatically clears TE to 0, EF is set to 1,
and an interrupt (if enabled by EIE = 1) is generated. TE and RE are never both set to 1 at the
same time. TE is cleared to 0 during RESET and IOSTOP mode.
SS2, 1, 0: Speed Select 2, 1, 0 (bits 2-0)—SS2, SS1 and SS0 select the CSIO transmit/
receive clock source and speed. SS2, SS1 and SS0 are all set to 1 during RESET. Table 13 lists
the CSIO Baud Rate selection.
Table 13. CSIO Baud Rate Selection
SS2 SS1 SS0 Divide Ratio
0
0
0
÷20
0
0
1
÷40
0
1
0
÷80
0
1
1
÷160
1
0
0
÷320
1
0
1
÷640
1
1
0
÷1280
1
1
1
External Clock Input
(less than ÷20)
After RESET, the CKS pin is configured as an external clock input (SS2, SS1, SS0 = 1).
Changing these values causes CKS to become an output pin and the selected clock is output
when transmit or receive operations are enabled.
PS014004-1106
Architecture