Z8018008VSG Datasheet, PDF (17/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
11
RXS—Clocked Serial Receive Data (input, active High). This line is the receiver data for the
CSIO channel. RXS is multiplexed with the CTS1 signal for ASCI channel 1.
ST—Status (output, active High). This signal is used with the M1 and HALT output to
decode the status of the CPU machine cycle.
Table 3. Status Summary
ST
HALT M1
0
1
0
1
1
0
1
1
1
0
X
1
0
0
0
1
0
1
Notes:
X = Reserved.
MC = Machine Cycle.
Operation
CPU Operation (1st opcode fetch)
CPU Operation (2nd opcode and 3rd opcode
fetch)
CPU Operation (MC except for opcode fetch)
DMA Operation
HALT Mode
SLEEP Mode (including SYSTEM STOP
Mode)
TEND0, TEND1—Transfer End 0 and 1 (outputs, active Low). This output is asserted active
during the most recent WRITE cycle of a DMA
operation. It is used to indicate the end of the block transfer. TEND0 is multiplexed with
CKA1.
TEST—Test (output, not in DIP version). This pin is for test and must be left open.
TOUT—Timer Out (output, active High). T_OUT is the pulse output from PRT channel 1. This
line is multiplexed with A18 of the address bus.
TXA0, TXA1—Transmit Data 0 and 1 (outputs, active High). These signals are the transmit-
ted data from the ASCI channels. Transmitted data changes are with respect to the falling
edge of the transmit clock.
TXS—Clocked Serial Transmit Data (output, active High). This line is the transmitted data
from the CSIO channel.
WAIT—Wait (input, active Low). WAIT indicated to the MPU that the addressed memory or
I/O devices are not ready for a data transfer. This input is sampled on the falling edge of T2
(and subsequent wait states). If the input is sampled Low, then the additional wait states are
inserted until the WAIT input is sampled high, at which time execution continues.
WR—WRITE (output, active Low, 3-state). WR indicated that the CPU data bus holds valid
data to be stored at the addressed I/O or memory location.
XTAL—Crystal (input, active High). Crystal oscillator connection. This pin must be left
open if an external clock is used instead of a crystal. The oscillator input is not a TTL level
PS014004-1106
Overview