Z8F082ASJ020EG Datasheet, PDF (69/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
52
Port A–C Input Data Registers
Reading from the Port A–C Input Data registers, shown in Table 29, return the sampled
values from the corresponding port pins. The Port A–C Input Data registers are read-only.
The value returned for any unused ports is 0. Unused ports include those missing on the 8-
and 28-pin packages, as well as those missing on the ADC-enabled 28-pin packages.
Table 29. Port A–C Input Data Registers (PxIN)
Bit
7
Field
PIN7
RESET
X
R/W
R
Address
X = Undefined.
6
PIN6
X
R
5
PIN5
X
R
4
3
PIN4
PIN3
X
X
R
R
FD2H, FD6H, FDAH
2
PIN2
X
R
1
PIN1
X
R
0
PIN0
X
R
Bit
Description
[7:0]
PxIN
Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Note: x indicates the specific GPIO port pin number (7–0).
Port A–D Output Data Register
The Port A–D Output Data Register, shown in Table 30, controls the output data to the pins.
Table 30. Port A–D Output Data Register (PxOUT)
Bit
Field
RESET
R/W
Address
7
POUT7
0
R/W
6
POUT6
0
R/W
5
4
3
2
POUT5 POUT4 POUT3 POUT2
0
0
0
0
R/W
R/W
R/W
R/W
FD3H, FD7H, FDBH, FDFH
1
POUT1
0
R/W
0
POUT0
0
R/W
Bit
Description
[7:0]
PxOUT
Port Output Data
These bits contain the data to be driven to the port pins. The values are only driven if the corre-
sponding pin is configured as an output and the pin is not configured for alternate function operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting
the corresponding Port Output Control Register bit to 1.
Note: x indicates the specific GPIO port pin number (7–0).
PS022827-1212
PRELIMINARY
GPIO Control Register Definitions