Z8F082ASJ020EG Datasheet, PDF (64/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
47
Port A–D Alternate Function Subregisters
The Port A–D Alternate Function Subregister, shown in Table 22, is accessed through the
Port A–D Control Register by writing 02H to the Port A–D Address Register. The Port A–
D Alternate Function subregisters enable the alternate function selection on pins. If dis-
abled, pins functions as GPIO. If enabled, select one of four alternate functions using
alternate function set subregisters 1 and 2 as described in the the Port A–D Alternate
Function Set 1 Subregisters section on page 50, the GPIO Alternate Functions section on
page 37 and the Port A–D Alternate Function Set 2 Subregisters section on page 51. See
the GPIO Alternate Functions section on page 37 to determine the alternate function asso-
ciated with each port pin.
Caution: Do not enable alternate functions for GPIO port pins for which there is no associated al-
ternate function. Failure to follow this guideline can result in unpredictable operation.
Table 22. Port A–D Alternate Function Subregisters (PxAF)
Bit
Field
RESET
R/W
Address
7
6
5
4
3
2
1
0
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
00H (Ports A–C); 01H (Port D); 04H (Port A of 8-pin device)
R/W
If 02H in Port A–D Address Register, accessible through the Port A–D Control Register
Bit
Description
[7:0]
AFx
Port Alternate Function Enabled
0 = The port pin is in normal mode and the DDx bit in the Port A–D Data Direction subregister
determines the direction of the pin.
1 = The alternate function selected through Alternate Function Set subregisters is enabled.
Port pin operation is controlled by the alternate function.
Note: x indicates the specific GPIO port pin number (7–0).
Port A–D Output Control Subregisters
The Port A–D Output Control Subregister, shown in Table 23, is accessed through the Port
A–D Control Register by writing 03H to the Port A–D Address Register. Setting the bits in
the Port A–D Output Control subregisters to 1 configures the specified port pins for open-
drain operation. These subregisters affect the pins directly and, as a result, alternate func-
tions are also affected.
PS022827-1212
PRELIMINARY
GPIO Control Register Definitions