Z8F082ASJ020EG Datasheet, PDF (186/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
169
ADC Calibration Data
Table 96. ADC Calibration Bits
Bit
7
6
5
4
3
2
Field
ADC_CAL
RESET
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Information Page Memory 0060H–007DH
Note: U = Unchanged by Reset. R/W = Read/Write.
1
U
R/W
0
U
R/W
Bit
[7:0]
ADC_CAL
Description
Analog-to-Digital Converter Calibration Values
Contains factory-calibrated values for ADC gain and offset compensation. Each of the ten
supported modes has one byte of offset calibration and two bytes of gain calibration. These
values are read by the software to compensate ADC measurements as described in the
Software Compensation Procedure Using Factory Calibration Data section on page 129.
The location of each calibration byte is provided in Table 97.
Info Page
Address
60
08
09
63
0A
0B
66
0C
0D
69
0E
0F
6C
10
11
6F
Memory
Address
FE60
FE08
FE09
FE63
FE0A
FE0B
FE66
FE0C
FE0D
FE69
FE0E
FE0F
FE6C
FE10
FE11
FE6F
Table 97. ADC Calibration Data Location
Compensation Usage
Offset
Gain High Byte
Gain Low Byte
Offset
Gain High Byte
Gain Low Byte
Offset
Gain High Byte
Gain Low Byte
Offset
Gain High Byte
Gain Low Byte
Offset
Gain High Byte
Gain Low Byte
Offset
ADC Mode
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended 1x Buffered
Single-Ended 1x Buffered
Single-Ended 1x Buffered
Single-Ended 1x Buffered
Single-Ended 1x Buffered
Single-Ended 1x Buffered
Differential Unbuffered
Reference Type
Internal 2.0 V
Internal 2.0 V
Internal 2.0 V
Internal 1.0 V
Internal 1.0 V
Internal 1.0 V
External 2.0 V
External 2.0 V
External 2.0 V
Internal 2.0 V
Internal 2.0 V
Internal 2.0 V
External 2.0 V
External 2.0 V
External 2.0 V
Internal 2.0 V
PS022827-1212
PRELIMINARY
Zilog Calibration Data