Z8F082ASJ020EG Datasheet, PDF (179/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
162
Trim Bit Data Register
The Trim Bid Data (TRMDR) Register contains the read or write data for access to the
trim option bits (Table 87).
Table 87. Trim Bit Data Register (TRMDR)
Bit
7
6
5
4
3
2
1
0
Field
TRMDR: Trim Bit Data
RESET
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
FF7H
Flash Option Bit Address Space
The first two bytes of Flash program memory at addresses 0000H and 0001H are reserved
for the user-programmable Flash option bits.
Flash Program Memory Address 0000H
Table 88. Flash Option Bits at Program Memory Address 0000H
Bit
7
6
5
4
3
Field WDT_RES WDT_AO OSC_SEL[1:0] VBO_AO
RESET
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
Address
Program Memory 0000H
Note: U = Unchanged by Reset. R/W = Read/Write.
2
FRP
U
R/W
1
Reserved
U
R/W
0
FWP
U
R/W
Bit
[7]
WDT_RES
[6]
WDT_AO
Description
Watchdog Timer Reset
0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer time-out causes a system reset. This setting is the default for unpro-
grammed (erased) Flash.
Watchdog Timer Always On
0 = Watchdog Timer is automatically enabled upon application of system power. Watch-
dog Timer can not be disabled.
1 = Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled,
the Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery. This
setting is the default for unprogrammed (erased) Flash.
PS022827-1212
PRELIMINARY
Flash Option Bit Address Space