Z8F082ASJ020EG Datasheet, PDF (187/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
170
Table 97. ADC Calibration Data Location (Continued)
Info Page
Address
12
13
30
31
72
14
15
32
33
75
16
17
34
35
78
18
19
36
37
7B
1A
1B
38
39
Memory
Address
FE12
FE13
FE30
FE31
FE72
FE14
FE15
FE32
FE33
FE75
FE16
FE17
FE34
FE35
FE78
FE18
FE19
FE36
FE37
FE7B
FE1A
FE1B
FE38
FE39
Compensation Usage
Positive Gain High Byte
Positive Gain Low Byte
Negative Gain High Byte
Negative Gain Low Byte
Offset
Positive Gain High Byte
Positive Gain Low Byte
Negative Gain High Byte
Negative Gain Low Byte
Offset
Positive Gain High Byte
Positive Gain Low Byte
Negative Gain High Byte
Negative Gain Low Byte
Offset
Positive Gain High Byte
Positive Gain Low Byte
Negative Gain High Byte
Negative Gain Low Byte
Offset
Positive Gain High Byte
Positive Gain Low Byte
Negative Gain High Byte
Negative Gain Low Byte
ADC Mode
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential Unbuffered
Differential 1x Buffered
Differential 1x Buffered
Differential 1x Buffered
Differential 1x Buffered
Differential 1x Buffered
Differential 1x Buffered
Differential 1x Buffered
Differential 1x Buffered
Differential 1x Buffered
Differential 1x Buffered
Reference Type
Internal 2.0 V
Internal 2.0 V
Internal 2.0 V
Internal 2.0 V
Internal 1.0 V
Internal 1.0 V
Internal 1.0 V
Internal 1.0 V
Internal 1.0 V
External 2.0 V
External 2.0 V
External 2.0 V
External 2.0 V
External 2.0 V
Internal 2.0 V
Internal 2.0 V
Internal 2.0 V
Internal 2.0 V
Internal 2.0 V
External 2.0 V
External 2.0 V
External 2.0 V
External 2.0 V
External 2.0 V
PS022827-1212
PRELIMINARY
Zilog Calibration Data