Z8F082ASJ020EG Datasheet, PDF (150/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
133
Output Data
The output format of the corrected ADC value is shown below.
MSB
LSB
svba9876543210––
The overflow bit in the corrected output indicates that the computed value was greater
than the maximum logical value (+1023) or less than the minimum logical value (–1024).
Unlike the hardware overflow bit, this is not a simple binary flag. For a normal (nonover-
flow) sample, the sign and the overflow bit match. If the sign bit and overflow bit do not
match, a computational overflow has occurred.
Input Buffer Stage
Many applications require the measurement of an input voltage source with a high output
impedance. This ADC provides a buffered input for such situations. The drawback of the
buffered input is a limitation of the input range. When using unity gain buffered mode, the
input signal must be prevented from coming too close to either V_SS or V_DD. See Table 139
on page 236 for details.
This condition applies only to the input voltage level (with respect to ground) of each dif-
ferential input signal. The actual differential input voltage magnitude may be less than
300 mV.
The input range of the unbuffered ADC swings from V_SS to V_DD. Input signals smaller
than 300 mV must use the unbuffered input mode. If these signals do not contain low out-
put impedances, they might require off-chip buffering.
Signals outside the allowable input range can be used without instability or device dam-
age. Any ADC readings made outside the input range are subject to greater inaccuracy
than specified.
ADC Control Register Definitions
This section defines the features of the following ADC Control registers.
ADC Control Register 0 (ADCCTL0): see page 134
ADC Control/Status Register 1 (ADCCTL1): see page 136
ADC Data High Byte Register (ADCD_H): see page 137
ADC Data Low Byte Register (ADCD_L): see page 137
PS022827-1212
PRELIMINARY
ADC Control Register Definitions