Z8F082ASJ020EG Datasheet, PDF (260/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
243
UART Timing
Figure 37 and Table 146 provide timing information for UART pins for the case where
CTS is used for flow control. The CTS to DE assertion delay (T1) assumes the Transmit
Data Register has been loaded with data prior to CTS assertion.
CTS
(Input)
DE
(Output)
T3
T1
TXD
(Output)
bit 7 parity stop
end of
stop bit(s)
start bit 0
bit 1
T2
Figure 37. UART Timing With CTS
Table 146. UART Timing With CTS
Parameter Abbreviation
UART
T₁
CTS Fall to DE output delay
T₂
DE assertion to TXD falling edge (start bit) delay
T₃
End of Stop Bit(s) to DE deassertion delay
Delay (ns)
Minimum
Maximum
2 * X_IN period 2 * X_IN period +
1 bit time
±5
±5
PS022827-1212
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical