Z8F082ASJ020EG Datasheet, PDF (102/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
85
The timer input can be used as a selectable counting source. It shares the same pin as the
complementary timer output. When selected by the GPIO Alternate Function registers,
this pin functions as a timer input in all modes except for the DUAL PWM OUTPUT
mode. For this mode, there is no timer input available.
Timer Control Register Definitions
This section defines the features of the following Timer Control registers.
Timer 0–1 Control Registers: see page 85
Timer 0–1 High and Low Byte Registers: see page 89
Timer Reload High and Low Byte Registers: see page 91
Timer 0–1 PWM High and Low Byte Registers: see page 92
Timer 0–1 Control Registers
The Timer Control registers are 8-bit read/write registers that control the operation of their
associated counter/timers.
Time 0–1 Control Register 0
The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1), shown
in Table 50, determine the timer operating mode. These registers each include a program-
mable PWM deadband delay, two bits to configure timer interrupt definition and a status
bit to identify if the most recent timer interrupt is caused by an input capture event.
Table 50. Timer 0–1 Control Register 0 (TxCTL0)
Bit
7
Field
TMODEHI
RESET
0
R/W
R/W
Address
6
5
TICONFIG
0
0
R/W
R/W
4
3
Reserved
0
0
R/W
R/W
F06H, F0EH
2
PWMD
0
R/W
1
0
INPCAP
0
0
R/W
R
Bit
[7]
TMODEHI
Description
Timer Mode High Bit
This bit, along with the TMODE field in the TxCTL1 Register, determines the operating
mode of the timer. This bit is the most significant bit of the Timer mode selection value. See
the description of the Timer 0–1 Control Register 1 (TxCTL1) for details about the full timer
mode decoding.
PS022827-1212
PRELIMINARY
Timer Control Register Definitions