Z8F082ASJ020EG Datasheet, PDF (126/282 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
109
byte indicating an overrun error, the Receive Data Register must be read again to clear the
error bits is the UART Status 0 Register. Updates to the Receive Data Register occur only
when the next data word is received.
UART Data and Error Handling Procedure
Figure 15 displays the recommended procedure for use in UART receiver interrupt service
routines.
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 15. UART Receiver Interrupt Service Routine Flow
Baud Rate Generator Interrupts
If the baud rate generator (BRG) interrupt enable is set, the UART Receiver interrupt
asserts when the UART Baud Rate Generator reloads. This condition allows the Baud
PS022827-1212
PRELIMINARY
Operation